The present invention relates generally to inverter circuits and, more particularly, to a system and method for substantially reducing the current flow during a transition period.
Buffer circuits are used to temporarily hold data while the data is being transferred or processed e.g., within a computer. Buffer circuits often include an inverter circuit that inverts an input data bit or input signal.
FIG. 1A is a schematic diagram of a conventional inverter 100. The inverter 100 includes an input node 102, where an input signal INa is applied and an output node 104, where an output signal OUTa can be taken. The inverter 100 also includes two MOS transistors 110, 112 and an output capacitor 108. The transistors are equal value transistors having opposite polarities in that transistor 110 is a PMOS transistor and transistor 112 is an NMOS transistor. A positive input signal INa is inverted to produce a negative output signal OUTa. Conversely, a negative input signal INa is inverted to produce a positive output signal OUTa. When the output signal OUTa is a low state, transistor 112 is conducting. Conversely, when the output signal OUTa is a high state, transistor 110 is conducting.
FIG. 1B is a timing diagram 150 for the operation of the conventional inverter 100. The inverter 100 does not switch instantaneously but rather gradually switches (or changes state) from high to low output signal OUTa in response to similarly gradually changing input signal INa. As shown in FIG. 1B, the input signal INa is shown as it transitions from a low state at time T1 to a high state at time T5. The output signal OUTa is shown transitioning from a high state at time T2 to a low state at time T4, in response to the transitioning state of the input signal INa.
As discussed above, when the output signal OUTa is a low state, transistor 112 is conducting and when the output signal OUTa is a high state, transistor 110 is conducting. Therefore, during the transition period between time T2 and time T4, peaking at about time T3, both transistor 110 and transistor 112 are conducting simultaneously. Because both transistor 110 and transistor 112 are conducting simultaneously a “transition short circuit current,” Is, flows from VDD, through transistor 110 and transistor 112 to ground. By way of example, the magnitude of the transition short circuit current, Is, can be about 220 mA at the peak at about time T3.
A transition short circuit current flow, Is, of 220 mA is greater than is necessary for the inverter 100 to invert the input signal INa. As a result, this excess current flow is wasted power. In view of the foregoing, there is a need for a technique that reduces the transition short circuit current flow and thereby reduces the amount of wasted power.